IBM unveiled a new chip architecture that fits nearly 100 billion transistors on a piece of silicon the size of a human fingernail, roughly twice the transistor density of its previous generation. The company is calling it the world's first sub-1 nanometer chip technology, branding the design as a 0.7-nanometer node — or 7 angstrom node, since one nanometer contains 10 angstroms. Projected gains over IBM's 2-nanometer node reach 50 percent higher compute performance or 70 percent greater energy efficiency, numbers aimed squarely at AI data centers.
The naming convention is marketing as much as physics. No transistor feature on the chip is actually below 1 nanometer — building reliable sub-nanometer features is not currently possible. Instead, IBM's nanostack architecture delivers the performance a theoretical sub-1nm chip would offer, by stacking transistors vertically in a staggered layout to cram more devices into the same area. Modern node names have been decoupled from physical dimensions since well before the 3nm and 2nm generations.
“It's not just an incremental step, it's a meaningful leap forward.”— Jay Gambetta, Director of IBM Research and IBM Fellow
Jay Gambetta, director of IBM Research and IBM Fellow, framed the work as a structural shift rather than another node tick. He described the design as pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy — the central constraint now facing operators of AI infrastructure.
Key facts
- 01IBM's nanostack architecture fits nearly 100 billion transistors on a fingernail-sized chip, roughly twice the density of its 2nm generation.
- 02The 0.7nm node — branded the 7 angstrom node — promises 50% more compute or 70% better energy efficiency than 2nm chips.
- 03A new staggered-channel SRAM bit cell cuts cell height by 40%, versus only a few percent of SRAM scaling between 3nm and 2nm.
- 04Each nanostack unit stacks two transistors, each built from three 5nm-thick nanosheets — about 15 rows of silicon atoms.
- 05Commercial production could begin within five years and most likely within a decade, IBM said at VLSI 2026 in Kyoto.
The basic building block of the nanostack architecture is two transistors stacked and bonded together. Each transistor uses three nanosheets, each 5 nanometers thick — about 15 rows of silicon atoms — with roughly 9 nanometers of vertical spacing between sheets. The approach builds directly on the nanosheet transistors IBM introduced with its 2-nanometer node in 2021, which has since become the template for every leading foundry's most advanced silicon.
Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, said nanosheet designs are now the foundation of frontier chip scaling. He noted that the architecture is used in most 3-nanometer chips today and all of the 2-nanometer chips currently in development at leading foundries — a list that includes Samsung in South Korea, Rapidus in Japan, and TSMC in Taiwan, the last of which independently developed its own nanosheet 2nm process.
“Nanosheet has become the foundation of the next generation of transistor scaling.”— Huiming Bu, Vice President of IBM Semiconductors Global R&D and IBM Research
The other headline number is SRAM scaling. IBM presented work at the VLSI 2026 symposium in Kyoto showing a 40 percent improvement in SRAM scaling using a staggered-channel design for the bit cells, the six-transistor memory storage units that drive fast read and write operations in AI workloads. Overall cell height drops 40 percent, freeing room for more on-die cache. Between the 3nm and 2nm generations, SRAM scaling improved only a few percent — a problem IBM is now claiming to leapfrog. Gambetta said the 40 percent gain will eventually industrialize itself in AI workflows, which demand higher bandwidth and efficiency.
IBM does not manufacture commercial chips. It licenses and partners — Rapidus is mass-manufacturing the company's 2nm nanosheet design in Japan, and a separate partnership with Samsung covers related technology. The company declined to name a manufacturing partner for the new sub-1nm node. Bu said commercial production could begin within the next five years and most likely within a decade, replacing nanosheet as the mainstream design across CPUs and GPUs.
“Within a decade, this will become another mainstream that we have invented and helped industry to transform.”— Huiming Bu, Vice President of IBM Semiconductors Global R&D and IBM Research
There are caveats worth keeping in mind. IBM's 50 percent and 70 percent figures are projections from technical reports, not yields from production silicon, and the path from a research demonstration to a foundry running 100-billion-transistor chips at acceptable defect rates is where most node transitions actually stall. TSMC's, Samsung's, and Rapidus's own roadmaps for sub-2nm production are already aggressive and have slipped before. A five-year window for sub-1nm commercial volume would be optimistic by any historical standard.
The strategic point for the AI buildout is straightforward. Hyperscalers are not constrained by transistor count alone — they're constrained by power delivery, cooling, and SRAM-bound inference bottlenecks. A node that delivers 70 percent better energy efficiency and 40 percent more on-die cache against today's frontier silicon, if it ships on anything close to IBM's timeline, would change the economics of AI inference at scale. IBM does not capture that revenue directly, but it sets the architectural template that Rapidus, Samsung, and eventually TSMC will be racing to manufacture — and that's a stronger commercial position than building the chips itself.
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