TSMC said today it is expanding CoWoS-L advanced packaging capacity to 230,000 wafers per year by the end of 2027, a tripling from current levels, in an effort to relieve the supply bottleneck that has constrained Nvidia's Blackwell GPU delivery. The commitment comes via a signed long-term agreement with Nvidia covering multiple design nodes and product generations through 2029.
CoWoS-L is the packaging layer where Nvidia's H200, B100, and upcoming Rubin GPUs are assembled—essentially the final step before a chip ships to customers. This step is disproportionately expensive and complex; while TSMC can manufacture 7-nanometer logic in massive volume, CoWoS assembly is labor-intensive and thermally challenging. Capacity has been the true constraint on Nvidia supply, not silicon production.
The expansion is also a direct competitive advantage for Nvidia over AMD. AMD's MI350X GPUs use conventional BGA packaging and are easier to scale, but they lack the performance density of Nvidia's interposer-based designs. TSMC's CoWoS-L bet is a bet that Nvidia's architecture dominance is durable and worth locking supply around.
Key facts
- 01TSMC. A key thread of reporting in this story.
- 02Nvidia. A key thread of reporting in this story.
- 03Packaging. A key thread of reporting in this story.
The timeline matters: 230,000 wafers per year from end-2027 is roughly 2.8x current capacity by mid-2028, right as Nvidia's Rubin generation enters production. This forward commitment gives Nvidia price visibility and supply certainty heading into 2027, while locking TSMC's capacity and capturing packaging margin that Nvidia competitors cannot match.
The agreement also subtly signals that Moore's Law and node shrinking are no longer the primary vectors for GPU performance. Instead, packaging density, memory bandwidth, and systemic design are winning. TSMC is betting billions on becoming the packaging company for AI, not just the logic foundry.
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