Nvidia is now using its Vera CPU to design the next generation of Nvidia CPUs and GPUs, with early testing showing up to 1.5x higher performance on key verification and simulation workloads. The chip carries 88 custom Nvidia Olympus cores, an LPDDR5X memory subsystem, and the second-generation Nvidia Scalable Coherent Fabric — a configuration tuned for the latency-sensitive, memory-hungry jobs that dominate electronic design automation. Nvidia disclosed the deployment in a company blog post on July 26, 2026, framing it as a strategic shift in how the world's largest AI silicon vendor builds its own future parts.
The 1.5x gain is measured against Nvidia's prior EDA infrastructure on the same core counts, and it lands on two of the most compute-intensive stages of modern chip development: formal verification and functional simulation. Nvidia is running the workloads on Vera clusters, including one already installed at its Portland data center. Cadence and Synopsys, the two dominant EDA vendors, are collaborating with Nvidia on the optimization work.
Cadence Jasper, the formal verification platform that uses machine learning to hunt bugs early in the design cycle, hit the 1.5x mark on selected workloads. Synopsys VCS, which simulates and validates chip designs before fabrication, showed the same 1.5x figure using an identical core count in Nvidia's tests. Both tools live at the CPU-bound end of the EDA stack, where per-core throughput and memory latency dictate how fast an engineering team can iterate.
“While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance.”— Ivan Goldwasser, Nvidia
Key facts
- 01Nvidia's Vera CPU is delivering up to 1.5x higher performance on selected EDA verification and simulation workloads in early testing.
- 02Vera packs 88 custom Nvidia Olympus CPU cores paired with LPDDR5X memory and the second-generation Nvidia Scalable Coherent Fabric.
- 03Cadence Jasper (formal verification) and Synopsys VCS (functional simulation) are the two production EDA tools showing the 1.5x gain.
- 04Nvidia is deploying Vera clusters, including at its Portland data center, across the workflows building its next CPUs and GPUs.
- 05The next-generation Rosa CPU, powered by the Nvidia Rigel core, is queued to follow Vera on the roadmap.
The framing matters because GPU-accelerated EDA has been an industry storyline for several years, and Nvidia itself has been its loudest proponent. But large portions of verification and digital implementation still run on CPUs, and the throughput of those runs sets the pace of tapeout. A 1.5x improvement compounds across thousands of regression jobs and shortens the window between architectural exploration and manufacturable silicon.
Vera is the CPU Nvidia designed to pair with its data-center GPUs, and repurposing it as the workhorse for its own engineering compute farms creates a tight vertical loop. Nvidia's next CPUs and GPUs are being verified on Nvidia CPUs, running EDA tools tuned for Nvidia's memory hierarchy and fabric. That kind of co-design was previously the province of Apple and, in narrower ways, Google and Amazon — vendors that build custom silicon and run their own workloads on it.
The company also disclosed the next step on the roadmap: a Rosa CPU built around the Nvidia Rigel core, positioned to succeed Vera and continue the internal EDA push. Nvidia has not shared a timeline for Rosa. The company plans to detail more of the work at DAC 2026, the industry's main EDA conference, and at Nvidia GTC Berlin running October 20-22.
The counterweight is that 1.5x on selected workloads is not the same as 1.5x across an entire design flow. Formal verification and functional simulation are two important stages, but tapeout involves synthesis, place-and-route, static timing analysis, and physical verification — some of which have different bottlenecks. Nvidia has not published broader benchmark data, and neither Cadence nor Synopsys has released independent numbers. The Portland deployment is real; the generalization to every EDA workload is not yet demonstrated.
“By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next.”— Ivan Goldwasser, Nvidia
For the broader AI chip market, the more interesting signal is competitive. Nvidia's dominance in AI training silicon rests on iteration speed as much as raw architecture, and any structural reduction in verification cycle time widens the gap with AMD, Intel, and the custom-silicon efforts at hyperscalers. If Vera-on-Vera design loops shave weeks off each generation's schedule, the compounding effect on Nvidia's roadmap cadence is more consequential than the 1.5x figure itself. The company is turning its product into its own factory floor, and the rest of the industry will have to price that in.
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